Kontakt
Wie einkaufen
Versand
Kaufberater
VHDL Modeling for Digital Design Synthesis
Englisch
471 b
Bis zu 30 Tage Rückgaberecht
Kunden kauften auch
/
Hardcover
14.69
€
/
Karte
7.90
€
VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.
Informationen zum Buch
Englisch
Kategorie
Verschenken Sie dieses Buch noch heute
Es ist ganz einfach
1 Legen Sie das Buch in Ihren Warenkorb und wählen Sie den Versand als Geschenk 2 Wir schicken Ihnen umgehend einen Gutschein 3 Das Buch wird an die Adresse des beschenkten Empfängers geliefertDas könnte Sie auch interessieren
/
Broschur
31.99
€
/
Broschur
14.09
€
/
Hardcover
252.49
€
Hallo! Ich bin Libroamiko, dein Buchberater.
Wie kann ich dir helfen?