FPGA DESIGN

The field-programmable gate array has quietly become one of the most important devices in modern electronics. It sits inside the base station that carries this sentence to your phone, inside the camera that inspects a thousand bottles a minute on a production line, inside the satellite payload that cannot be recalled for repair, and inside the data-centre accelerator card that searches a database faster than any processor could. What makes the FPGA remarkable is not simply that it is fast; it is that its hardware is written rather than manufactured. A designer describes a circuit in a text file, presses a button, and a few minutes later a piece of silicon has physically become that circuit.
This book is about learning to write hardware well. It is intended for undergraduate and postgraduate students of electronics, electrical, computer science and instrumentation engineering, for practising engineers migrating from software or from board-level design, and for researchers who need a reconfigurable platform for their experiments.
What this book tries to do differently
Three convictions shaped every chapter.
Architecture first, then language. A great many FPGA designs are inefficient because they were written by someone who did not know what a look-up table, a carry chain or a block RAM actually is. Chapters 2 and 3 therefore open the device and look inside before a single line of HDL is written. Once the reader knows that the fabric offers a six-input look-up table and a dedicated carry chain, code such as a wide comparator or a pipelined adder stops being mysterious and starts being predictable.
Two languages, side by side. Industry uses both VHDL and Verilog, and a graduate who knows only one is at a disadvantage. Rather than choosing a side, this book teaches both: Chapter 5 develops VHDL, Chapter 6 develops Verilog and SystemVerilog, and from Chapter 7 onward most major examples appear in both languages so that the reader can read either dialect fluently and translate between them.
Everything is synthesisable and tested. Every listing in this book was written to be synthesised onto a real device, not merely to illustrate syntax. Where a construct simulates but does not synthesise, the text says so plainly. Each design unit is accompanied by the reasoning that a reviewer would apply: is the reset strategy correct, will this infer a latch, does this cross a clock domain safely, what does the timing report say.
How the book is organised
The nineteen chapters fall into six natural groups.

• Foundations (Chapters 1-4). What programmable logic is, what is inside a modern FPGA, the digital-design principles that matter for the fabric, and the complete design flow from specification to configured device.
• Languages (Chapters 5-6). VHDL and Verilog/SystemVerilog for synthesis, taught through the structures a designer actually writes: entities, processes, always blocks, packages and parameterisation.
• Building blocks (Chapters 7-10). Combinational design and synthesis, sequential design and finite state machines, on-chip memory and FIFOs, and arithmetic using the DSP slice.
• Making it work (Chapters 11-13). Clocking and timing constraints, static timing analysis, metastability and clock-domain crossing, and the physical I/O and serial interfaces that connect the device to the world.
• Systems and verification (Chapters 14-16). Embedded processors and AXI-based SoC design, verification and testbench construction, and optimisation for area, speed and power.
• Practice (Chapters 17-19). Reliability, configuration and security; a sequence of complete, laboratory-ready projects; and a concluding survey of high-level synthesis and where the technology is heading.